Problems of conventional semiconductor integrated circuits will be described below by taking the following three arrangements as examples.
The first example is a bipolar transistor. An ECL (Emitter Coupled Logic) circuit is available as the most typical circuit using a bipolar transistor, and its switching time t.sub.pd is represented by the following relation: EQU t.sub.pd .varies.r.sub.bb' [ACT.sub.TC1 +C.sub.d1 ]+V.sub.S .multidot.(C.sub.TS1 +C.sub.de1)/I.sub.CS
where
r.sub.bb' : the base resistance of an input transistor PA1 A: the voltage amplification factor of a current switching circuit PA1 V.sub.S : the logic amplitude voltage PA1 C.sub.TC1 : the base-collector junction capacitance of the input transistor PA1 C.sub.d1 : the diffusion capacitance and the emitter-base junction capacitance of the input transistor PA1 I.sub.CS : the current amount of the input transistor PA1 C.sub.TS1 : the collector-side parasitic capacitance of the input transistor PA1 C.sub.de1 : the diffusion capacitance of an output emitter-follower transistor. PA1 forming an insulating film, which can be selectively dry-etched with respect to an insulative compound to be subsequently formed, on a surface of a first film, PA1 exposing at least a portion of a side portion of the insulating film to form a conductive material layer on a surface adjacent to the surface of the first film, PA1 forming an insulative compound film on a surface of the conductive material layer by a surface reaction with the conductive material layer, and PA1 dry-etching the insulating film to expose the surface of the first film, and forming a second film required for a device arrangement on the surface of the first film. PA1 film formation of the conductive material, PA1 formation of an insulating layer on a surface of the conductive material, PA1 removal of the SiO.sub.2 layer, and PA1 formation of the emitter thin film are all performed in an apparatus without exposing a wafer to the outer air. PA1 film formation of the conductive material, PA1 formation of a non-impurity-doped SiO.sub.2 layer on a portion of the conductive material, PA1 formation of an insulating layer on a surface of the conductive material, PA1 removal of only the impurity-doped SiO.sub.2 layer, and PA1 formation of the emitter thin film are performed. PA1 film formation of source and drain semiconductors, PA1 film formation of the conductive material, PA1 formation of a non-impurity-doped SiO.sub.2 layer on a portion of the conductive material, PA1 formation of an insulating layer on the surface of the conductive material, PA1 removal of only the impurity-doped SiO.sub.2 layer, and PA1 formation of an insulating interlayer and contact holes and formation of source, gate, and drain electrodes are performed. PA1 formation of an impurity-doped SiO.sub.2 film on an insulating interlayer, PA1 formation of a resist pattern of wiring, PA1 etching of the impurity-doped SiO.sub.2 using the resist pattern, PA1 formation of a resist pattern of contact holes, PA1 dry etching of the insulating interlayer, PA1 film formation of the conductive material for constituting the wiring member, PA1 formation of the insulative compound film on the surface of the wiring member, and PA1 removal of the impurity-doped SiO.sub.2 layer are performed.
As is apparent from the above relation, in case of a low-current region, i.e., a region of small I.sub.CS for the ECL circuit, a delay time is determined by a collector response time in the second term of relation (1). On the other hand, a base response time in the first term in the relation becomes dominant in a region where I.sub.CS is large. That is, reduction in r.sub.bb' and C.sub.TC and that in the diffusion capacitance, i.e., an improvement in an f.sub.T value is an important factor of increasing an operation speed.
To realize a high operation speed, a transistor using an SST (Super-Self-aligned process Technology) as shown in FIG. 15 is currently proposed. Referring to FIG. 15, reference numeral 201 denotes a p-type semiconductor substrate; 202, a p.sup.+ -type semiconductor isolation region for isolating adjacent elements; 203, an n.sup.+ -type buried layer (n.sup.+ -BL); 204, an n-type epitaxial layer; 205, a field oxide layer; 206, an Si.sub.3 N.sub.4 film; 207, a p-type base region; 208, a p.sup.+ -type polycrystalline Si base electrode; 209, an n.sup.+ -type emitter region; 210, an n.sup.+ -type polycrystalline Si emitter electrode; and 211, 212, and 213, base, emitter, and collector electrodes, respectively, each consisting of a metal.
FIG. 16 shows the emitter and base regions of this conventional example in an enlarged scale. As is apparent from FIG. 16, since the p.sup.+ -type polycrystalline Si base electrode 208 for a base contact is formed close to the emitter region 209, an external base current is reduced.
The above conventional example, however, has the following problems.
(1-1) A natural oxide film 214 is present in the interface between the n.sup.+ -type polycrystalline Si layer 210 and the p-type base region 207 of the single-crystal epitaxial layer 204 to cause a variation in bipolar characteristics (especially, an emitter ground current amplification factor).
The emitter region 209 in this structure is normally called a DOPOS (Doped Poly Silicon) emitter which is formed by doping an impurity in the n.sup.+ -type poly silicon layer 210 into the portion 209 of the epitaxial layer by thermal diffusion. However, since a wafer must be temporarily exposed to the outer air before formation of the n.sup.+ -type poly Si layer 210 on the p-type base region 207, the natural oxide film 214 is formed on the p-type base region 207. The natural oxide film 214 is nonuniform because the process control is impossible. As a result, the diffusion of the impurity into the p-type base region 207 becomes nonuniform.
To settle the matter radically, therefore, a process not forming any natural oxide film must be adopted. In the current circumstances, however, since a contact hole patterning step for the emitter region 209 is necessary before formation of the n.sup.+ -type poly Si layer 210, the upper surface of the p-type base region 207 of the epitaxial layer 204 is inevitably exposed to the outer air and a natural oxide film is formed on the surface.
(1-2) When the contact hole formation step (hole formation) for forming the emitter region 209 is performed by dry etching, the base region 207 present below the emitter region 209 is damaged.
Although wet etching may be performed as etching free from a damage, since the size of a contact hole is inevitably increased when the wet etching is used, no micropatterned emitter region can be formed. Although a dry etching method causing no damage has been developed, the method is currently still unsatisfactory.
(1-3) A base resistance is still high to interfere with a high-speed operation.
That is, although an external base resistance is reduced in the bipolar transistor using the SST described above as compared with conventional transistors, it is still high because poly Si is used as the material of the base electrode 208.
Problems of a MOSFET will be described below.
(2-1) Degradation in a drain current I.sub.P and g.sub.m (.ident..differential.I.sub.P /.differential.I.sub.G) becomes significant due to a parasitic resistance as the degree of micropatterning is increased.
FIG. 17 shows calculated values and measured values in a relationship between an effective channel length (abscissa) and a drain current (ordinate) obtained in an LDD (Lightly Doped Drain) structure which is used most often among conventional micropatterned MOSFETs. The calculation is performed using an equivalent circuit model formed in consideration of a parasitic resistance and speed saturation. As is apparent from FIG. 17, as the effective channel length approaches 0.2 .mu.m, the parasitic resistance is increased, and current reduction in a nonsaturated region becomes significant.
(2-2) In a conventional MOSFET structure in which a source.multidot.drain region is formed by a diffusion layer, a channel length is significantly decreased in a micropatterned region.
FIG. 18 shows a change in threshold voltage (ordinate) as a function of a channel length L (abscissa) using a depth X.sub.j of a source.multidot.drain diffusion layer as a parameter. As shown in FIG. 18, in an ordinary MOSFET, reduction in threshold value becomes significant because the channel length is decreased when the depth X.sub.j is large. However, since a source.multidot.drain diffusion layer of a conventional MOSFET is formed by ion implantation using a gate as a mask, the minimum value of X.sub.j is at most about 0.1 .mu.m, and it is difficult to form a source.multidot.drain portion having a depth smaller than this value.
(2-3) Selection of a gate material is considerably limited.
In a conventional MOSFET, a source.multidot.drain diffusion layer is formed by ion implantation using a gate as a mask. Therefore, a gate material is required to satisfy the following conditions.
(1) The gate material must have an ion-implantation resistance.
(2) Since a heat treatment is performed at a temperature of 550.degree. C. or more to activate the source.multidot.drain formed by ion implantation, the material must withstand a temperature of 550.degree. C. or more.
(3) The gate material must allow formation of an insulating layer around the gate portion in order to prevent a leakage current between the gate and the source.multidot.drain.
(4) The gate material must have a low resistance to realize a high-speed operation.
(5) The gate material must have a predetermined work function to suppress reduction in threshold value caused by a short channel length. If Al, for example, is used as the gate material to achieve a low resistance, the problem of heat resistance described in item (2) above is satisfied.
Lastly, problems in conventional wiring will be described below. FIG. 19 is a view showing conventional wiring steps, in which reference numeral 215 denotes a substrate or a wafer layer, e.g., a p-type semiconductor layer. Reference numeral 216 denotes a field oxide film; 217, a diffusion layer for contact with respect to wiring, which is an n.sup.+ -type semiconductor layer in this example; 218, an insulating layer such as SiO.sub.2 formed by a CVD apparatus; 219, a wiring metal; and 220, a resist for patterning the wiring metal 219. FIG. 19(a) is a view showing a step in which resist patterning is finished. The resultant wafer is conveyed into an RIE (Reactive Ion Etching) apparatus, and its metal wiring is etched as shown in FIG. 19(b). Referring to FIG. 19(b), reference numeral 222 denotes an etching residue of the wiring metal. The etching residues 222 are produced because a metal enters microspaces on the surface of the insulating layer 218 or the resist 220 is scattered in an RIE atmosphere when the wafer is exposed to the atmosphere and the scattered resist components adhere on the metal surface to form masks. These residual metal components cause a leakage current.
FIG. 19(c) shows a step of removing the resist obtained by patterning the wiring metal after the etching. As shown in FIG. 19(c), removal of the resist and washing are generally performed using an organic substance such as trichloroethylene. However, residues 223 of the resist are produced in such a method. Although a method (so-called O.sub.2 ashing) of leaving a wafer to stand in an oxygen plasma to remove a resist may be used, a damage is produced because the wafer is left to stand in the plasma.
As described above, the conventional wiring steps have the following problems.
(3-1) A wiring metal remains at a microlevel on the surface of an insulating layer, and a leakage current is flowed through this residual metal.
(3-2) A resist used in patterning of wiring is not perfectly removed, and an organic impurity remains on a wafer.
(3-3) When O.sub.2 ashing is performed in resist removal, a damage caused by a plasma is produced inside a wafer.
As a result, in conventional techniques, even if attempts are made to keep clean surface conditions on various film surfaces (e.g., a semiconductor surface and an insulating layer surface) having important effects on device characteristics, mixing of an impurity caused by a natural oxide film or a resist residue cannot be prevented. Therefore, there exists no device in which neither a natural oxide film nor an impurity remains on the surface of each film surface.